It has long been a goal of research and industry to produce compound semiconductive devices which are integratable and are competitive with silicon devices across a much greater range of applications than the presently available high-speed or highly specialized types of devices. Technologies utilizing GaAs Metal-Semiconductor Transistors (MESFETs) and Heterostructure Field Effect Transistors (HFETs) have not yet been able to produce reliable ultra-fast VLSI circuits with acceptable yields.
Such devices are, nonetheless, attractive because it appears possible to achieve very low power-dissipation-times-delay products for such devices, which generally have very high electron mobilities.
It can be shown that a decrease in the power-delay product requires decreasing device size or decreasing the power supply voltage. Decrease in device size is limited by the fabrication technology and by the need to generate enough current to drive interconnecting circuits. The power supply or bias voltage is limited by the requirement of a sufficiently large noise margin of a logic gate.
Increasingly, it has appeared that noise margins are influenced by such parameters as source and drain series resistances and the voltage spans of the knees of the input-output voltage characteristics. The higher the electron mobilities, the lower the last-referenced voltage knee should be. However, gate leakage currents have remained a serious problem, as has also the variation of the threshold voltage from wafer to wafer.
In the article by R. Zuleeg et al., "VLSI Circuit Design and Performance of GaAs J-FET Technology", 1989 URSI International Symposium on Signals, Systems and Electronics, pp. 187-190 (published by Union Radio-Scientifique International, 1989, Federal Republic of Germany), a JFET technology is proposed to address the problem of the gate leakage current. Nevertheless, we do not find that solution to yield devices that are fast enough because of a low device transconductance.